The present invention relates to a method of fabricating a semiconductor element, for example, a resistor in polysilicon between two areas of polysilicon in a polycide element. The present invention also relates to a semiconductor element. The present invention has particular application in the fabrication of semiconductor resistors for use in random access memories.
In semiconductor devices such as static random access memories which incorporate memory cells, it is desirable to use silicide, e.g. tungsten silicide, as an interconnect level instead of polysilicon since silicide has higher inherent electrical conductivity and thus permits the fabrication of higher performance devices. One disadvantage of silicide is that it is not possible to control the conductivity of the silicide by doping the silicide with impurities. Consequently, it is not possible to create resistors or diodes in polycide, "polycide" being a term known in the semiconductor fabrication art for a multi-layered structure having a layer of silicide on top of a layer of polysilicon. Another disadvantage of silicide is that when silicide is deposited over polysilicon it contaminates the polysilicon and makes it more highly conductive. If the silicide is subsequently etched away, the underlying polysilicon remains contaminated and cannot be used to fabricate load devices. Accordingly, in order to fabricate load devices in semiconductor devices, which include silicide interconnect, it is necessary to ensure that the silicide is not directly in contact with the load devices.
It is known to provide a static random access memory (SRAM) cell which consists of two pass gate transistors, two cross coupled latch transistors and two load devices. The load devices may be resistors and the SRAM cell may have the configuration which is shown in FIG. 2 of US-A-4471374 which is assigned to Inmos Corporation. Such a memory cell is referred to as a 4T2R SRAM cell since it comprises four transistors and two resistors. However, the 4T2R memory cell does not employ silicide interconnect. An attempt has been made to fabricate a SRAM cell which does employ silicide interconnect and therefore has higher performance. However, due to the disadvantages of silicide described above it was necessary to fabricate the load devices as transistors, rather than resistors, resulting in a six transistor (6T) SRAM cell. This arrangement suffers from the disadvantage that a six transistor SRAM cell has a large area which leads to a reduction in the memory capacity of a memory of prescribed dimensions.
EP-A-0192871 which is in the name of Inmos Corporation discloses a method of forming a polysilicon resistor in a polycide line in which a barrier material isolates a polysilicon resistor from an overlayer of silicide which forms two polycide interconnect regions on opposed sides of the resistor. However, this method has inherent alignment tolerances which results in a memory cell of relatively large size.
Accordingly, there is a need for SRAM cells, which employ silicide interconnect and incorporate load devices, which can be fabricated to a smaller size than the above-described known devices.
EP-A-0167249 which is also in the name of Inmos Corporation discloses a method of fabricating a resistor in polysilicon, the resistor having a structure which electrically resembles back-to-back diodes and is referred to as RABID, RABID being an acronym meaning Rapid Annealed Boron Implanted Diode. The disclosed resistor can be readily fabricated and has a low thermal activation energy. However, there is no teaching of how to incorporate such a RABID structure into a polycide semiconductor element.
Accordingly, there is also a need for RABID load devices in polycide semiconductor elements.
In Solid State Electronics, Volume 30, No. 4, pp. 361-363, 1987, I. Abdel - Moteleb and L. Young disclose a self-aligned gate process for fabricating a GaAs MESFET using a polyamide layer. However, that article does not relate to semiconductor elements employing silicide interconnect.